1) Field of the Invention
This invention relates generally to fabrication of memory cells and more particularly to a method for simultaneously fabricating vertical bipolar transistors, CMOS transistors and a CMOS dynamic random access memory (DRAM) cell.
2) Description of the Prior Art
There is a need to build complementary metal oxide semiconductor (CMOS) transistors, memory cells, and bipolar transistors on the same semiconductor chip. CMOS and bipolar transistors have different electrical properties and for certain applications a combination of both CMOS and bipolar devices are required. It is known that bipolar devices have a lower variation of threshold voltage (Vth), a high driving capability and better mismatch characteristics than CMOS devices. Bipolar devices can improve the sensing amplifier speed and driving power which are critical in high speed integrated circuits.
However, to integration of CMOS and bipolar devices typically requires a buried layer and a post-epitaxy processes. These extra process add significant costs and the post-epitaxy process reduce the product yields. It is desirable to used a combination of Bipolar and CMOS devices in semiconductor chips, but the increased manufacturing costs and reduced yields make wide spread implementation impracticable.
Semiconductor technologies have dramatically increased the circuit density on a chip. The miniaturized devices built in and on semiconductor substrate are very closely spaced and their packing density has increased significantly. More recent advances in photolithographic techniques, such as phase-shifting masks, and self-aligning process steps have further reduced the device sized and increased circuit density. This has lead to ultra large scale integration (ULSI) with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With this improved integration, some circuit elements experience electrical limitation due to their down sizing.
One such circuit element experiencing electrical limitations is the array of storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field effect transistor (MOS-FET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of the memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Many of the prior art methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. For example, most process use an epitaxy layer and require additional steps and costs. Therefore, it is very desirable to develop processes that are as simple as possible and also provide methods for fabrication CMOS and Bipolar transistors in the same process.
There is a challenge to develop methods of manufacturing simultaneously both bipolar and CMOS devices on the same chip. The process should minimize the manufacturing costs and maximize the device yields. The process should not require an epitaxy layer. In particular, there is a challenge to develop a method for fabricating simultaneously CMOS transistors, CMOS memory cells and Bipolar devices which minimizes the number of photoresist masking operations and hot process steps. Also the process should provide maximum process tolerance to maximize product yields. There is also a need to minimize the resistance between the base and collector in the bipolar transistor.